Marguerite Silas
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# Cleveland Institute of Technology – Technology and Computer Science
Below is a concise, student‑friendly guide to the core technology concepts you’ll encounter in our curriculum. It covers the "why" behind each topic, how it’s used in real life, and where you can find additional resources.
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1. Digital Electronics
What? Why? Real‑World Use
Logic gates (AND, OR, NOT, NAND, NOR, XOR) + flip‑flops & multiplexers Build the brain of every digital device – they perform Boolean algebra on binary data. Smartphones, cars’ ECUs, home automation systems, industrial PLCs
Key Concept: Truth tables → map input combinations to outputs
> Pro Tip: Try a simple truth‑table exercise in paper or Excel before moving to a simulator.
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1️⃣ Verilog / SystemVerilog – "C" for hardware
Synthesis‑ready example (2‑bit adder)
// 2‑bit ripple carry adder
module add2b(
input 1:0 A, B,
output 1:0 SUM,
output CARRY_OUT
);
assign CARRY_OUT, SUM = A + B; // single line synthesisable
endmodule
`assign` – continuous assignment (combinational logic).
Synthesis tool will generate a carry‑chain logic.
Testbench skeleton
module tb;
reg 1:0 A, B;
wire 1:0 SUM;
wire CARRY_OUT;
add2b dut(.A(A), .B(B), .SUM(SUM), .CARRY_OUT(CARRY_OUT));
initial begin
$dumpfile("wave.vcd"); $dumpvars(0,tb);
A=0; B=0; #10;
// apply stimuli...
end
endmodule
3. Using a Mixed‑Language Flow
Verilog (or SystemVerilog) for RTL.
C/C++ to generate stimulus vectors and check results.
Use OpenMP or `std::thread` if the test harness is CPU‑bound.
Call Verilog simulator via system calls (`vcs`, `iverilog`, `verilator`).
Example C++ testbench:
#include
#include "simulator_api.h" // Provided by your simulator
int main()
Sim sim("rtl.v");
for (int i = 0; i <100; ++i)
sim.set_input(i);
sim.clock();
int out = sim.get_output();
if (out != expected(i)) std::cerr <<"Mismatch at " <<i <<"
";
Compile with:
g++ -o tb testbench.cpp -lverilator
./tb
4. Tips for Effective Debugging
Tip Why it matters
Use waveforms (e.g., GTKWave, ModelSim). Visualizing signals is often faster than parsing logs.
Add assertions (`assert property`). Catches violations early and points to exact time.
Segment tests into smaller units. Isolates failure point; easier to reason about each case.
Document expected behavior in comments or a spec file. Prevents ambiguity when reviewing test results.
Keep simulation deterministic (seed the RNG). Reproduces failures reliably for debugging.
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6. Quick Reference Cheat Sheet
Item Command / Code Snippet What It Does
Run all tests `cargo test` Compiles and executes every function annotated with `#test`.
| Run a single test | `cargo test ` | Only runs the specified test. |
| Show detailed output for failing tests | `cargo test -- --nocapture` | Keeps stdout/stderr from being captured, useful for debugging prints. |
| Run with debug assertions on (e.g., `assert!`) | `cargo test -Zunstable-options --debug-assertions` | Enables checks that might be disabled in release mode. |
| Check code style and formatting | `cargo fmt --check` | Verifies that the code is formatted according to Rustfmt rules. |
| Lint with Clippy | `cargo clippy -- -D warnings` | Runs Clippy, treating all lints as errors (`-D warnings`). |
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6. Summary & Checklist
Item Status
Project structure: src/, tests/ directories ✅
Main.rs: `fn main() {}` ✅
Library.rs: Empty ✅
Test file: `tests/` with `mod test` and a trivial test ✅
Cargo.toml: package metadata, dependencies ✅
Run tests: `cargo test` passes ✅
Optional: Add more tests, features, or documentation ?
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7. Next Steps (optional)
Write real library functions in `lib.rs`.
Add integration tests that use the public API.
Use Cargo features to enable optional dependencies.
Publish on crates.io if you plan to share it.
Feel free to ask if you need help expanding this starter or adding more functionality!
